NDLI: An efficient pipelined VLSI implementation of rank order filter

Content Provider	IEEE Xplore Digital Library
Author	Chun-Ta Chen Liang-Gee Chen Tzi-Dar Chiueh Jue-Hsuan Hsiao
Copyright Year	1994
Description	Author affiliation: Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan (Chun-Ta Chen; Liang-Gee Chen; Tzi-Dar Chiueh; Jue-Hsuan Hsiao)
Abstract	An efficient pipelined VLSI implementation of rank order filter based on the ordering property is proposed. In the previous works, this filter required many iterations in the bit-serial implementation of the positive Boolean function (PBF) and used a large number of counters, comparators and many AND-OR logic array inputs in a parallel architecture to output an M-th order sample. This limited the real-time applications for large window size. Based on the ordering property of the values of the elements in the m-array, we proposed a pipeline architecture to fold the parallel data flow in order to reduce the hardware complexity without loss of performance. The proposed design can also realize the concurrent search method for the PBF to output an M-th order sample. Compared with previous works, the hardware complexity is reduced from O(2/sup r/) to O(2/sup r/2/) area-time complexity and the latency approaches that of a parallel implementation.<>
Starting Page	630
Ending Page	633
File Size	321967
Page Count	4
File Format	PDF
ISBN	078031865X
DOI	10.1109/SIPNN.1994.344832
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-04-13
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Filters Boolean functions Search methods Pipelines Very large scale integration Hardware Performance loss Parallel architectures Logic arrays Counting circuits
Content Type	Text
Resource Type	Article

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