NDLI: Comparison of three different architectures for MOS-compatible quadratic synapses

Content Provider	IEEE Xplore Digital Library
Author	Fakhraie, S.M. Smith, K.C. Xu, J.M.
Copyright Year	1994
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada (Fakhraie, S.M.; Smith, K.C.; Xu, J.M.)
Abstract	Inspired by the harmony between the basic functional elements of biological neural networks and their natural operating media, we have been seeking for ways to implement artificial neural networks (ANNs) using the intrinsic functionality of the most commonly available devices in an electronics technology, in contrast to the method of hardware-compilation of software-simulation modules. In the case of MOS technology, we employ a quadratic functional equation similar to that found in standard MOS transistors to implement synapses in ANNs. A structure has been proposed in to implement a MOS device with externally-controllable threshold voltage to be employed as a synapse. In the present work, we develop and compare practical architectures within which these synapses can be utilized optimally. A simulator and proper training algorithms have been developed to simulate different hardware-based architectures.<>
Starting Page	483
Ending Page	486
File Size	340602
Page Count	4
File Format	PDF
ISBN	078031865X
DOI	10.1109/SIPNN.1994.344786
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-04-13
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computer architecture Artificial neural networks Parallel processing CMOS technology Threshold voltage Hardware Voltage control Equations MOSFETs MOS devices
Content Type	Text
Resource Type	Article

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