NDLI: Design of AXI bus based MPSoC on FPGA

Content Provider	IEEE Xplore Digital Library
Author	Fu-ming Xiao Dong-sheng Li Gao-ming Du Yu-kun Song Duo-li Zhang Ming-lun Gao
Copyright Year	2009
Description	Author affiliation: Institute of VLSI Design, Hefei University of Technology, China (Fu-ming Xiao; Dong-sheng Li; Gao-ming Du; Yu-kun Song; Duo-li Zhang; Ming-lun Gao)
Abstract	While the computational core is becoming faster and faster, the communication efficiency between the processors has become a bottleneck which limits the performance of multiprocessor system-on-chip (MPSoC). This paper focuses on design and implementation of AXI bus protocol-based MPSoC architecture. Firstly, the RTL models of 4 NIOS II processors using AXI communication architecture are developed. Then the MPSoC was implemented in Altera Stratix II EP2S180 FPGA. Lastly, the performance was evaluated using matrix operation benchmark and compared with previous in-house designed architecture. Experiments showed that the proposed prototype could run at 100 MHz requiring 8963 Adaptive Look-up Table (ALUTs) and the maxim speedup ratio can be up to 3.81, and performs better than the traditional bus (AHB bus) and 2-D mesh NoC architecture.
Starting Page	560
Ending Page	564
File Size	238772
Page Count	5
File Format	PDF
ISBN	9781424438839
DOI	10.1109/ICASID.2009.5277006
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-08-20
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	NoC MPSoC AXI bus Access protocols Master-slave Very large scale integration Table lookup Multiprocessing systems Integrated circuit manufacture Network-on-a-chip Prototypes Computer architecture Field programmable gate arrays Speedup Ratio
Content Type	Text
Resource Type	Article

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