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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Dai Zi-bin Qin Fan Yang Xiao-hui |
| Copyright Year | 2009 |
| Abstract | Computing the inverse of a number in finite fields GF(p) or GF(2n) is equally important for cryptographic applications. A novel scalable and unified architecture for a Montgomery inversion hardware that operates in both GF(p) and GF(2n) is proposed. The scalable design is the novel modification performed on the fixed hardware to make it occupy a small area and operate with better or similar speed, and it takes less number of clock cycle as the fixed datapath is large and can also achieve high clock frequency. Finally this work has been verified by modeling it in Verilog-HDL, implementing it under 0.18μm CMOS technology. The reault indicates that our work has advanced performance than other works. |
| Starting Page | 206 |
| Ending Page | 209 |
| File Size | 367151 |
| Page Count | 4 |
| File Format | |
| ISBN | 9780769536798 |
| DOI | 10.1109/ICIE.2009.208 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2009-07-10 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Computer architecture CMOS technology Elliptic curve cryptography Frequency Hardware Iterative algorithms Polynomials Electronic mail Montgomery inversion algorithm Scalable hardware architecture FPGA ASIC Galois fields Clocks |
| Content Type | Text |
| Resource Type | Article |
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