NDLI: ePUMA: A novel embedded parallel DSP platform for predictable computing

Content Provider	IEEE Xplore Digital Library
Author	Jian Wang Sohl, J. Kraigher, O. Dake Liu
Copyright Year	2010
Description	Author affiliation: Department of Electrical Engineering, Linköping University, Sweden (Jian Wang; Sohl, J.; Kraigher, O.; Dake Liu)
Abstract	In this paper, a novel parallel DSP platform based on master-multi-SIMD architecture is introduced. The platform is named ePUMA [1]. The essential technology is to use separated data access kernels and algorithm kernels to minimize the communication overhead of parallel processing by running the two types of kernels in parallel. ePUMA platform is optimized for predictable computing. The memory subsystem design that relies on regular and predictable memory accesses can dramatically improve the performance according to benchmarking results. As a scalable parallel platform, the chip area is estimated for different number of co-processors. The aim of ePUMA parallel platform is to achieve low power high performance embedded parallel computing with low silicon cost for communications and similar signal processing applications.
File Size	908852
File Format	PDF
ISBN	9781424463671
e-ISBN	9781424463701
DOI	10.1109/ICETC.2010.5529952
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-06-22
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Embedded computing data permutation Costs multi-bank memory SIMD architecture Concurrent computing Signal processing algorithms Digital signal processing Computer architecture Parallel processing Silicon Kernel chip multi-processor conflict-free memory access Coprocessors
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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