NDLI: Design of fixed-point high-performance FFT processor

Content Provider	IEEE Xplore Digital Library
Author	Li Wenqi Wang Xuan Sun Xiangran
Copyright Year	2010
Description	Author affiliation: Communication University of China, Beijing, China (Li Wenqi; Wang Xuan; Sun Xiangran)
Abstract	This paper, based on the complexity and hardware requirement of conventional FFT algorithms, analyses the architecture of radix-4 Single-Path Delay Feedback (SDF) in DIF and present an efficient FFT processor for real-time applications. A test bench is built up comparing Signal to Quantization Noise Ratio (SQNR) performances of the processors with a float-point model and fixed-point one. Several values of I/O word length and twiddle factor word length are implemented, to investigate the quantization effect of fixed-point arithmetic with limited precision derived from rounding or truncation errors, for enhancing the output performance. The simulation tests and an implementation of 1024-point FFT targeted on XC5VSX50T FPGA, show that the proposed FFT processor has a high computational frequency and hence suitable for usual OFDM wireless applications.
File Size	1056333
File Format	PDF
ISBN	9781424463671
e-ISBN	9781424463701
DOI	10.1109/ICETC.2010.5529796
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-06-22
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Algorithm design and analysis Performance evaluation Quantization twiddle factor Delay pipeline Keywords-FFT radix-4 Feedback fixed-point Signal processing Hardware Testing Signal to noise ratio Fixed-point arithmetic
Content Type	Text
Resource Type	Article

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