NDLI: Accelerating text-based plagiarism detection using GPUs

Content Provider	IEEE Xplore Digital Library
Author	Jiffriya, M. Jahan, M.A. Gamaarachchi, H. Ragel, R.G.
Copyright Year	2015
Description	Author affiliation: Dept. of Comput. Eng., Univ. of Peradeniya, Peradeniya, Sri Lanka (Gamaarachchi, H.; Ragel, R.G.) \|\| Post Grad. Inst. of Sci., Univ. of Peradeniya, Peradeniya, Sri Lanka (Jiffriya, M.; Jahan, M.A.)
Abstract	Plagiarism is known as an unauthorized use of other's contents in writing and ideas in thinking without proper acknowledgment. There are several tools implemented for text-based plagiarism detection using various methods and techniques. However, these tools become inefficient while handling a large number of datasets due to the process of plagiarism detection which comprises of a lot of computational tasks and large memory requirement. Therefore, when we deal with a large number of datasets, there should be a way to accelerate the process by applying acceleration techniques to optimize the plagiarism detection. In response to this, we have developed a parallel algorithm using Compute Unified Device Architecture (CUDA) and tested it on a Graphics Processing Unit (GPU) platform. An equivalent algorithm is run on CPU platform as well. From the comparison of the results, CPU shows better performance when the number and the size of the documents are small. Meantime, GPU is an effective and efficient platform when handling a large number of documents and high in data size due to the increase in the amount of parallelism. It was found out that for our dataset, the performance of the algorithm on the GPU platform is approximately 6x faster than CPU. Thus, introducing GPU based optimization algorithm to the plagiarism detection gives a real solution while handling a large number of data for inter-document plagiarism detection.
Starting Page	395
Ending Page	400
File Size	716009
Page Count	6
File Format	PDF
ISBN	9781509017416
e-ISBN	9781479918768
DOI	10.1109/ICIINFS.2015.7399044
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-12-18
Publisher Place	Sri Lanka
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	NVIDIA Instruction sets Graphics processing units vector space model CPU thread GPU Phased arrays CUDA hashing strategy Parallel processing Jaccard similarity block Acceleration Yttrium Kernel
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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