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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Li Yan Li Xian-yao Gu Ping-ping Zhao Hong-jie Cheng Ping |
| Copyright Year | 2010 |
| Abstract | The plan to design hardware real-time operating system based on FPGA is presented and the harden of the $\mu$ C/OS-II is done, in order to resolve the problem that the real-time operating system kernel takes a lot of system resources and reduces the schedulability of application. The major function module of RTOS is composed of four parts the management of the event flag group (EFG), the semaphore management, the task management and the clock management. The task control block (TCB) is realized based on chip registers as well as the task scheduler and the semaphore management of hard-core are built by combinational circuits, both of them give full play to the potential of the multi-task parallelism. The hardware system is described by VHDL, simulated through the ISE 8.2 and realized on FPGA. Simulation results show that the hardware realization of the system reduces the running time efficiently and makes it possible to apply in time-critical systems. |
| Starting Page | 825 |
| Ending Page | 828 |
| File Size | 361469 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424463886 |
| e-ISBN | 9781424463893 |
| DOI | 10.1109/ETCS.2010.633 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-03-06 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Real time systems task management Circuit simulation Registers Combinational circuits Hardware real-time operating system VHDL Operating systems Hardware Time factors Kernel Field programmable gate arrays Clocks semaphore management |
| Content Type | Text |
| Resource Type | Article |
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