NDLI: Area-efficent power clamp circuit using gate-coupled structure for Smart Power ICs

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A 9-context optically reconfigurable gate array

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An active-RC filter with variable bandwidth and channel-selectivity characteristics

CMOS OTA compensating transconductance linearity with PMOS path

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A low power ZigBee baseband processor

A generalized framework for energy savings in real-time multiprocessor systems

Power reduction controll for multicores in OSCAR multigrain parallelizing compiler

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DFM optimization of standard cells considering random and systematic defect

Parametric yield-aware sign-off flow in 65/45nm

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An accurate analysis of a VCO voltage regulator

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The development of an energy-awared mobile 3D graphics SoC with real-time performance/energy monitoring and control

System anlaysis of power-aware H.264/AVC encoder based on fast inter prediction

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Reconfigurable motion estimation architecture design on H.264/AVC for power aware mobile application

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Scheduling considering bit level delays

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an optimized rendering algorithm for hardware implementation of openVG 2D vector graphics

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Non-invasive direct probing for on-chip voltage measurement

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Reducing cost of frequency binning: An effective and efficient approach

Segmented scan architecture using segment grouping for test cost reduction

A new approach for circuit design optimization using Genetic Algorithm

μCRL: A Computer Science based approach for specification and verification of hardware circuits

On-line learning based dynamic thermal management for multicore systems

Automatic mapping of application to coarse-grained reconfigurable architecture based on high-level synthesis techniques

Implementing the component-based software engineering in embedded systems

Millimeter-wave CMOS power amplifiers in common-source MOSFETs

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Investigation of forward body bias effects on TSPC RF frequency dividers in 0.18 μm CMOS

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Design of optical fiber sensor driving IC for structure monitoring system

A 26mW dual-mode RF receiver for GPS/Galileo with L1/L1F and L5/E5a bands

The dependability analysis of LIN network for adaptive front-lighting system

Area-efficent power clamp circuit using gate-coupled structure for Smart Power ICs

An improved RF MOSFET model including scalable gate resistance and external inductances

A L1-Band RF receiver for GPS aplication in 0.13um CMOS technology

Scalable modeling of spiral inductor in 0.13μm RF CMOS process

Area-efficent power clamp circuit using gate-coupled structure for Smart Power ICs

Content Provider	IEEE Xplore Digital Library
Author	Dong-Jun Kim Ju-Ho Park Sang-Gyu Park
Copyright Year	2008
Description	Author affiliation: Div. of Electron. & Comput. Eng., Hanyang Univ., Seoul (Dong-Jun Kim; Ju-Ho Park; Sang-Gyu Park)
Abstract	Area-efficient ESD (Electro Static Discharge) power clamp using gate-coupled structure for Smart Power technology is proposed. The use of Big-FET parasitic Capacitance results in the reduction of the total size of the circuit when compared to the Darlington scheme and RC triggered circuits. The performance of the proposed ESD power clamp was successfully verified in a 0.35 um 60 V BCD (bipolar CMOS DMOS) process by TLP (Transmission Line Pulse) measurements.
File Size	97640
File Format	PDF
ISBN	9781424425983
DOI	10.1109/SOCDC.2008.4815664
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-11-24
Publisher Place	South Korea
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Pulse measurements gate-coupled structure Electrostatic discharge CMOS process Clamps smart power technology power clamp circui Power transmission lines Power measurement Distributed parameter circuits CMOS technology electrostatic discharge (ESD) Power integrated circuits Parasitic capacitance
Content Type	Text
Resource Type	Article

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