NDLI: A Sigma-Delta class D audio power amplifier in 0.35μm CMOS technology

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A 9-context optically reconfigurable gate array

A Sigma-Delta class D audio power amplifier in 0.35μm CMOS technology

Fast RSSI circuit using novel power detector for wireless communication

An active-RC filter with variable bandwidth and channel-selectivity characteristics

CMOS OTA compensating transconductance linearity with PMOS path

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Design of a geometry engine for mobile 3D graphics

Hybrid architecture of full-search block-matching motion estimation circuit for MPEG-4 encoder

Improved frame selector for multi-reference motion estimation

The development of an energy-awared mobile 3D graphics SoC with real-time performance/energy monitoring and control

System anlaysis of power-aware H.264/AVC encoder based on fast inter prediction

Energy-saving techniques for low-power graphics processing unit

Reconfigurable motion estimation architecture design on H.264/AVC for power aware mobile application

TunableVP: A Tunable Virtual Platform for easy SoC design space exploration

Energy-effective design & implementation of an embedded VLIW DSP

Speeding up SoC virtual platform simulation by data-dependency aware virtual synchronization

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High performance NoC architecture for two hidden layers BP Neural Network

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The proposed on-chip bus system with GALDS topology

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Scheduling considering bit level delays

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an optimized rendering algorithm for hardware implementation of openVG 2D vector graphics

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Automatic mapping of application to coarse-grained reconfigurable architecture based on high-level synthesis techniques

Implementing the component-based software engineering in embedded systems

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Design of optical fiber sensor driving IC for structure monitoring system

A 26mW dual-mode RF receiver for GPS/Galileo with L1/L1F and L5/E5a bands

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An improved RF MOSFET model including scalable gate resistance and external inductances

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A Sigma-Delta class D audio power amplifier in 0.35μm CMOS technology

Content Provider	IEEE Xplore Digital Library
Author	Junle Pan Libin Yao Yong Lian
Copyright Year	2008
Description	Author affiliation: Dept. of Electr. & Comput. Eng., VLSI Lab. Nat. Univ. of Singapore, Singapore (Junle Pan; Libin Yao; Yong Lian)
Abstract	This paper presents a single chip class D audio power amplifier realized in a 0.35 mum CMOS technology. This chip consists of a high-linear single-loop feed-forward Sigma-Delta modulator with three level quantizer and a full H-bridge output stage. The three-level quantizer effectively reduces the switching activity of the output stage, especially when the input signal amplitude is low, hence improves the power efficiency. Direct feedback from H-bridge output improves the linearity of the amplifier. With a 3.3-V supply voltage and 4-Ohm load, the amplifier can deliver maximum 1-W output power with THD less than 0.8% at 8 kHz and reaches a maximum power efficiency more than 80%.
File Size	412145
File Format	PDF
ISBN	9781424425983
DOI	10.1109/SOCDC.2008.4815561
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-11-24
Publisher Place	South Korea
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	High power amplifiers ΔΣ modulation Pulse amplifiers Pulse width modulation Quantization Delta-sigma modulation Topology Power amplifiers feedforward CMOS technology Feedforward systems 1.5bit quantization Signal to noise ratio
Content Type	Text
Resource Type	Article

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