NDLI: The design of FIR filter base on improved DA algorithm and its FPGA implementation

Content Provider	IEEE Xplore Digital Library
Author	Shunwen Xiao Yajun Chen Peng Luo
Copyright Year	2010
Description	Author affiliation: College of Physics and Electronic information, China West Normal University, CWNU, Nanchong, Sichuan, 637002, China (Shunwen Xiao; Yajun Chen; Peng Luo)
Abstract	When the DA (distributed arithmetic) algorithm is directly applied in FPGA (field programmable gate array) to realize FIR (finite impulse response) filter, it is difficult to achieve the best configuration in the coefficient of FIR filter, the storage resource and the computing speed. According to this problem, the paper provides the detailed analysis and discussion in the algorithm, the memory size and the look-up table speed. Also, the corresponding optimization and improvement measures are discussed and the concrete hardware realization of the circuit is presented. The design based on Altera EP2C5T144C8 chips is synthesized under the integrated environment of QUARTUSII7.1. The results of simulation and test show that this method greatly reduces the FPGA hardware resource and the high speed filtering is achieved. The design has a big breakthrough compared to the traditional FPGA realization.
Starting Page	589
Ending Page	591
File Size	120927
Page Count	3
File Format	PDF
ISBN	9781424455850
e-ISBN	9781424455867
DOI	10.1109/ICCAE.2010.5451677
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-02-26
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Algorithm design and analysis FIR filter FPGA Table lookup DA algorithm Distributed computing Semiconductor device measurement Integrated circuit measurements Finite impulse response filter Hardware Concrete Field programmable gate arrays Arithmetic
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in