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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Zhongqi Li Xiang Ling Jianhao Hu |
| Copyright Year | 2009 |
| Abstract | As the scale of System-on-Chip (SoC) grows rapidly in recent years, the communication burden between on-chip elements becomes much greater than before. Network-on-Chip (NoC) has been proposed as a solution for this issue. However, it is difficult to use mathematical models to analyze the application-specific NoC with various topologies, switching architectures and routing algorithms. Existing simulators tend to divide the whole simulation flow into independent stages. This division causes inaccurate simulation results in packet delay, traffic load, power consumption, etc. In this paper, we propose a top-down Message passing Interface (MPI) style hierarchical simulation framework, MSNS (MPI Style NoC Simulator), for the NoC systems. It integrates the layers from application down to network infrastructure. This simulation framework can achieve more reliable and accurate simulation results for application-specific NoC system. It is based on SystemC to adapt to both high level abstraction and RTL (Register Transfer Level) implementation. In order to achieve the generality, MPI standard for parallel processes is used as the communication interface. Both a specific parallel computation system and the NoC infrastructure can be evaluated in this simulation framework. The more accurate simulation results can be achieved with dynamic traffic in MSNS. The availability of MSNS is proved with case study. |
| Starting Page | 609 |
| Ending Page | 614 |
| File Size | 353287 |
| Page Count | 6 |
| File Format | |
| ISBN | 9780769535012 |
| DOI | 10.1109/CMC.2009.67 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2009-01-06 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Algorithm design and analysis Computational modeling VLSI Network-on-Chip Telecommunication traffic Routing Communication switching Delay Network topology Simulation Network-on-a-chip System-on-a-chip Mathematical model SystemC |
| Content Type | Text |
| Resource Type | Article |
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