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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Na Ra Yang Gilsang Yoon Jeonghwan Lee Intae Hwang Cheol Hong Kim Sung Woo Chung Jong Myon Kim |
| Copyright Year | 2009 |
| Abstract | Minimizing the communication delay is one of the most important design considerations in System-on-a-Chip (SoC) design for mobile systems. In this paper, we present a bus interface design technique, called Efficient Bus Interface (EBI), to reduce the communication delay between the Intellectual Property (IP) core and the memory connected through AMBA3 AXI bus for mobile systems. Several mobile systems require huge multimedia data in the memory to be transferred to the IP core through bus. The EBI is designed to reduce the memory access time by using double buffering, open row access, and bank interleaving. According to our simulations, the proposed EBI improves the performance of the target system by up to 49%. |
| Starting Page | 606 |
| Ending Page | 608 |
| File Size | 213742 |
| Page Count | 3 |
| File Format | |
| ISBN | 9780769535012 |
| DOI | 10.1109/CMC.2009.297 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2009-01-06 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Computer interfaces Protocols Mobile communication Control systems System-on-a-Chip Delay Bridges Embedded System Bus Interface System performance Mobile System AMBA Intellectual property System-on-a-chip Mobile computing |
| Content Type | Text |
| Resource Type | Article |
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