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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Shrestha, M. Lihao Xu |
| Copyright Year | 2013 |
| Description | Author affiliation: Dept. of Comput. Sci., Wayne State Univ., Detroit, MI, USA (Shrestha, M.; Lihao Xu) |
| Abstract | Flash memory is a non-volatile, non-mechanical data storage technology that stores data by trapping charge and can be reused by freeing the trapped charge with an internal erase operation. When flash memory cells are erased, there is a considerable negative impact on the longevity and performance of the device. To defer and minimize these erasures, a floating code is able to store variable updates as cell increments. A (n, q, k) floating code uses an array of n cells with q levels to store k binary variables. In this paper, we investigate the poset (partially ordered sets) structures derived from the various states of the n cells and k variables. These posets have fundamentally different structures that makes designing floating codes a challenge, most notably their structure of their vertex covers. Based on the poset structure, we present a new floating code for l = 2 and arbitrary q, k and n ∈ {k, k+1}, or arbitrary n, q and k = 2 that is optimal for single cell increments and has a deficiency of O(qk), the best possible deficiency. We present an algorithm for constructing the floating code and prove that the algorithm produces a valid floating code. |
| Sponsorship | IEEE Cont. Syst. Soc. |
| Starting Page | 621 |
| Ending Page | 628 |
| File Size | 1188805 |
| Page Count | 8 |
| File Format | |
| e-ISBN | 9781479934102 |
| DOI | 10.1109/Allerton.2013.6736583 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-10-02 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Vectors |
| Content Type | Text |
| Resource Type | Article |
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