NDLI: Using Early Power and Timing Estimations of Massively Heterogeneous Computation Platforms to Create Optimized HPC Applications

Content Provider	IEEE Xplore Digital Library
Author	Knocke, P. Gorgen, R. Walter, J. Helms, D. Nebel, W.
Copyright Year	2014
Description	Author affiliation: OFFIS-Inst. for Inf. Technol., Oldenburg, Germany (Knocke, P.; Gorgen, R.; Walter, J.; Helms, D.) \|\| Univ. of Oldenburg, Oldenburg, Germany (Nebel, W.)
Abstract	The ever rising energy and accordingly cooling demands are a major hurdle for the scalability of today's supercomputers. We are challenged with the need to increase computation performance to cope with the rising complexity of calculations on the one hand and the need to keep the energy/cooling demand stable or in the best case even to reduce it. Recently, one widely discussed way to do this is the integration of heterogeneous computation devices into the supercomputer systems as these tend to have a far better performance/energy ratio for large classes of applications. The obvious drawback of heterogeneous systems is the additional design complexity for the software development in order to efficiently use these devices in terms of performance as well as power. For this reason we propose a flow, which assists the software developer at design time, offering immediate power- and performance-estimation. Such approaches are already known in the embedded world, helping there to select between different design possibilities, and will be used to get the best possible performance from a massively heterogeneous computation platform, while still keeping the energy consumption in mind.
Starting Page	162
Ending Page	169
File Size	381241
Page Count	8
File Format	PDF
ISBN	9780769552491
DOI	10.1109/EUC.2014.31
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-08-26
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Performance evaluation Computer aided software engineering Multicore processing Computational modeling Estimation Hardware Timing Performance analysis Resource management Kernel System analysis and design
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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