NDLI: A Scalable Server Architecture for Next-Generation Heterogeneous Compute Clusters

Content Provider	IEEE Xplore Digital Library
Author	Griessl, R. Peykanu, M. Hagemeyer, J. Porrmann, M. Krupop, S. Berge, M.V.D. Kiesel, T. Christmann, W.
Copyright Year	2014
Description	Author affiliation: Cognitronics & Sensor Syst. Group, Bielefeld Univ., Bielefeld, Germany (Griessl, R.; Peykanu, M.; Hagemeyer, J.; Porrmann, M.) \|\| Christmann Informationstechnik + Medien GmbH & Co. KG, Ilsede, Germany (Krupop, S.; Berge, M.V.D.; Kiesel, T.; Christmann, W.)
Abstract	Increasing the energy efficiency of today's high-performance computing systems requires new approaches that go beyond homogeneous architectures, which primarily target maximum performance per node. Heterogeneous architectures that can be tailored towards the specific needs of a particular application are a promising alternative to state-of-the-art server systems. In this paper, we present a novel highly-scalable server architecture that seamlessly integrates variable combinations of general purpose CPUs, embedded CPUs, FPGAs, and GPUs. Embedded CPUs based on the latest ARM Cortex-A15 devices with integrated embedded GPUs are combined with FPGA-based reconfigurable SoCs, which can be used for application-specific hardware acceleration. A dedicated monitoring network enables continuous control and fine-grained observation of all relevant system parameters. Communication between the compute nodes is established by a flexible multi-level interconnect that can be adapted to various Ethernet and Infiniband standards. The communication facilities are further enhanced by direct high-bandwidth, low-latency links between the embedded FPGA-based reconfigurable SoCs.
Starting Page	146
Ending Page	153
File Size	2109772
Page Count	8
File Format	PDF
ISBN	9780769552491
DOI	10.1109/EUC.2014.29
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-08-26
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Heterogeneous Cluster Server ARM-based Microserver FPGA Switches Servers Standards Compute Cluster High-Speed Serial Interconnect Computer architecture Exascale Hardware Monitoring Field programmable gate arrays
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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