NDLI: Using an Analytical Model of Shared Caches for Selecting the Optimal Parallelization Scheme

Content Provider	IEEE Xplore Digital Library
Author	Andrade, D. Fraguela, B.B. Doallo, R.
Copyright Year	2012
Abstract	Multicores are now the norm. Their cache hierarchy has often a last level shared cache. The performance of this shared cache during the execution of multithreaded applications depends on the parallelization scheme followed. For example, critical parameters for the performance of parallelized loops are the number of threads and the block size. The selection of the optimal scheme in a compiler can be guided using heuristics or the execution time. Heuristics can be imprecise, while an execution time guided search is very time-consuming. This paper shows the usage of an analytical model to predict the cache behavior of shared caches during the execution of multithreaded applications that have been parallelized at loop level. The model predicts the number of misses generated by a given code when different number of threads or block sizes are used. The execution time of the codes analyzed is highly correlated to the number of misses generated in the shared cache, thus, the prediction of the model is a powerful tool to select the best parallelization scheme for them.
Starting Page	588
Ending Page	594
File Size	275386
Page Count	7
File Format	PDF
ISBN	9781467316316
DOI	10.1109/ISPA.2012.88
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-07-10
Publisher Place	Spain
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Analytical models Multicore processing shared cache Instruction sets analytical modeling Predictive models Data structures Dynamic scheduling cache memories parallel applications Mathematical model
Content Type	Text
Resource Type	Article

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