NDLI: Development of a HART compatible HART line powered communication module

Content Provider	IEEE Xplore Digital Library
Author	Dudacek, K. Ledvina, J. Vavricka, V.
Copyright Year	2014
Description	Author affiliation: Dept. of Comput. Sci. & Eng., Univ. of West Bohemia in Pilsen, Pilsen, Czech Republic (Dudacek, K.; Ledvina, J.; Vavricka, V.)
Abstract	The HART protocol is a specification designed for industrial process automation and control. In this paper we provide the design and implementation of the communication module with HART protocol. The primary objective of the designed hardware is to minimize current consumption so that the module is powered by a 4-20 mA current loop. The employed parts have also been selected with regard to the minimum current consumption. Another requirement for the proposed module was its galvanic isolation from the measuring device. Communication between the HART communication module and the measuring device is implemented as shared access to the I2C EEPROM and FRAM. The basic idea for the software development was to use real-time operating system and divide the program into separate processes with mutual communication. As an operating system we choose FreeRTOS, which is able to perform processes (tasks) on the basis of events as well as to use preemptive scheduling. By a suitable proposal of hardware and software we managed to present a flexible solution that meets the former requirements.
Starting Page	75
Ending Page	78
File Size	278723
Page Count	4
File Format	PDF
ISBN	9788026102762
ISSN	18037232
e-ISBN	9788026102779
DOI	10.1109/AE.2014.7011672
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-09-09
Publisher Place	Czech Republic
Access Restriction	Subscribed
Rights Holder	University of West Bohemia
Subject Keyword	Protocols Power demand Algorithms MSP430F5437A Current measurement EPROM FreeRTOS Random access memory Real-time systems HART
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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