NDLI: A new communication mechanism for multi-core systems in industrial design

Content Provider	IEEE Xplore Digital Library
Author	Gang Han Jia Lu Baoliang Li Junhui Wang Guofu Wu Wenhua Dou
Copyright Year	2012
Description	Author affiliation: School of Computer Science, National University of Defense Technology, Changsha, Hunan 410073 P.R. China (Gang Han; Jia Lu; Baoliang Li; Junhui Wang; Guofu Wu; Wenhua Dou)
Abstract	In industrial design, multi-core systems are receiving more and more attention for their special characteristics as low power consumption, reliability and extensibility. Multi-core processors are usually designed in shared memory architecture and tasks on different cores run concurrently. The communication between tasks must be performed consistently, which means the access to shared communication buffer (or resource) should be atomic. Many mechanisms have been proposed for this purpose, e.g. wait-free and lock-based. However, different mechanisms show different performance on system schedulability and memory overhead. So, it would be a good choice to combine these mechanisms together, i.e. to protect different resources with different mechanisms. This is a variation of bin-packing problem, which is NP-complete. We propose a heuristic algorithm to select the communication mechanisms with minimum memory requirements executing within the time constraints. The experiment demonstrates that the heuristic provides close to optimal solutions and the proposed algorithm can significantly reduce the memory consumption of wait-free method, guaranteeing that all tasks complete before their deadlines.
Starting Page	1
Ending Page	4
File Size	150002
Page Count	4
File Format	PDF
ISBN	9781467309141
e-ISBN	9781467309158
DOI	10.1109/ICSSEM.2012.6340792
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-10-20
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Protocols Multicore processing Data consistency Memory management Industrial design Random access memory Real-time systems Time factors Data communication Automotive Optimization
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Real-Time Memory Controller for Embedded Multi-core System

A design approach for predictable and efficient multi-core processor for avionics

Task placement and selection of data consistency mechanisms for real-time multicore applications

Hardware support for resource partitioning in real-time embedded systems

Timing analysis of multi-mode applications on AUTOSAR conform multi-core systems

On the Suitability of Multi-Core Processing for Embedded Automotive Systems

Open event machine: A multi-core run-time designed for performance

Optimization of Multi-core Interconnection for WCET Analysis in Automotive Application

MemGuard: Memory bandwidth reservation system for efficient performance isolation in multi-core platforms

A new communication mechanism for multi-core systems in industrial design

Similar Documents

Real-Time Memory Controller for Embedded Multi-core System

A design approach for predictable and efficient multi-core processor for avionics

Task placement and selection of data consistency mechanisms for real-time multicore applications

Hardware support for resource partitioning in real-time embedded systems

Timing analysis of multi-mode applications on AUTOSAR conform multi-core systems

On the Suitability of Multi-Core Processing for Embedded Automotive Systems

Open event machine: A multi-core run-time designed for performance

Optimization of Multi-core Interconnection for WCET Analysis in Automotive Application

MemGuard: Memory bandwidth reservation system for efficient performance isolation in multi-core platforms

A new communication mechanism for multi-core systems in industrial design