NDLI: A low power bulk-driven MDAC synapse

Content Provider	IEEE Xplore Digital Library
Author	Laajimi, R. Hamdi, B. Ayari, N.
Copyright Year	2011
Description	Author affiliation: Electronic & Microelectronics' LAB. Monastir Tunisia (Laajimi, R.; Hamdi, B.; Ayari, N.)
Abstract	Efficient weight storage and multiplication are important design challenges which must be addressed in analog neural network implementations. Many schemes have been previously reported for implementation of synapses. In this paper we describe a buck driven Multiplier digital-to-analog converter (MDAC) circuit. We present a novel synapse circuit for analog neural networks. This circuit is a 6-bit Multiplier Digital to Analogue Converter (MDAC) synapse based on bulk-driven technology. The circuit has a small layout area (1200 μm2 using 0.18μm TSMC CMOS technology). The measured results are within ±0.5 LSB for DNL and ±0.4 LSB for INL, with 0.1 mW power dissipation at 0.75 V power supply and the silicon area is reduced by a factor of 35% with respect to conventional MDAC implementation.
Starting Page	1
Ending Page	5
File Size	1111836
Page Count	5
File Format	PDF
ISBN	9781457703157
ISSN	18037232
e-ISBN	9788070439302
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-09-07
Publisher Place	Czech Republic
Access Restriction	Subscribed
Rights Holder	University of West Bohemi
Subject Keyword	Layout Neurons Very large scale integration Multiplying DAC CMOS technology CMOS integrated circuits Low power Mirrors Bulk-driven technology Deep-N-Well Biological neural networks
Content Type	Text
Resource Type	Article

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