NDLI: Design and implementation of CORDIC processor for complex DPLL

Content Provider	IEEE Xplore Digital Library
Author	Mandal, A. Kaushik, B.K. Kumar, B. Agarwal, R.P.
Copyright Year	2011
Description	Author affiliation: Department of CSE & IT, Shobhit University, Meerut, India (Agarwal, R.P.) \|\| Department of Electronics and Computer Engineering, Indian Institute of Technology, Roorkee, India (Kaushik, B.K.; Kumar, B.) \|\| Electronic Engineering and Installation Unit, New Delhi, India (Mandal, A.)
Abstract	Now-a-days various Digital Signal Processing systems are implemented on a platform of programmable signal processors or on application specific VLSI chips. Coordinate Rotation Digital Computer (CORDIC) algorithm has turned out to be such kind of programmable signal processor. In recent times, it has been a widely researched topic in the field of vector rotated Digital Signal Processing (DSP) applications due to its simplicity. This paper presents the design of pipelined architecture for coordinate rotation algorithm for the computation of loop performance of complex Digital Phase Locked Loop (DPLL) in In-phase and quadrature channel receiver. The design of CORDIC in the vector rotation mode results in high system throughput due to its pipelined architecture where latency is reduced in each of the pipelined stage. For on-chip application, the area reduction in proposed design can is achieved through optimization in the number of micro rotations. For better loop performance of first order complex DPLL and to minimize quantization error, the numbers of iterations are also optimized.
Starting Page	1
Ending Page	5
File Size	181043
Page Count	5
File Format	PDF
ISBN	9781424478835
e-ISBN	9781424478828
DOI	10.1109/IICPE.2011.5728075
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-01-28
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Algorithm design and analysis Low pass filters Very large scale integration Digital Signal Processing CORDIC DPLL Equations Pipelined Architecture Loop performance Micro-rotation Signal processing algorithms Computer architecture Demodulation
Content Type	Text
Resource Type	Article

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