NDLI: The use of delay lines in a ring-oscillator-based combined true random number generator

Content Provider	IEEE Xplore Digital Library
Author	Jessa, M. Matuszewski, L.
Copyright Year	2012
Description	Author affiliation: Faculty of Electronics and Telecommunications, Poznan University of Technology, Poland (Jessa, M.; Matuszewski, L.)
Abstract	This paper presents a novel approach for the design of ring oscillators in a combined true random number generator (TRNG). We propose using delay elements made on carry4 primitives instead of series of inverters or latches in ring oscillators, which enables the construction of many high frequency ring oscillators with different nominal frequencies in the same field programmable gate array (FPGA). The output sequences produced by this type of TRNG pass all NIST 800-22 statistical tests for smaller numbers of ring oscillators than the constructions described in the literature. To assess the unpre-dictability of the output bits, the restarts mechanism, proposed in earlier papers, was used. Due to the number of ROs with different nominal frequencies and the method of construction of carry4 primitives, it is expected that the proposed TRNG is less sensitive to frequency injection attacks.
Starting Page	1
Ending Page	6
File Size	1277292
Page Count	6
File Format	PDF
ISBN	9781467317108
e-ISBN	9781467317115
e-ISBN	9781467317092
DOI	10.1109/ICSES.2012.6382232
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-09-18
Publisher Place	Poland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Latches Delay lines NIST Inverters Generators Delay Field programmable gate arrays
Content Type	Text
Resource Type	Article

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