NDLI: Open loop approach to design low voltage, 400 mV, 1.3 mW, 10 GHz CMOS class-B VCO

Content Provider	IEEE Xplore Digital Library
Author	Szczepkowski, G. Farrell, R.
Copyright Year	2012
Description	Author affiliation: CTVR - The Telecommunication Research Centre Callan Institute, National University of Ireland Maynooth, Ireland (Szczepkowski, G.; Farrell, R.)
Abstract	The paper presents a method for design of LC cross-coupled oscillators based on an open loop technique and its practical application leading to a high frequency CMOS oscillator prototype. Thanks to the proposed approach, the main circuit parameters such as loaded quality factor (responsible for phase noise performance of LC oscillator) and steady-state oscillation amplitude, can be extracted without the necessity of time consuming transient simulations. The presented method is not technology specific and allows fast calculations under changing bias conditions. The proposed 130 nm CMOS prototype operates at 10 GHz from a 400m V power supply achieving an average SSB phase noise of −110 dBc/Hz at 1 MHz offset from the carrier and a fractional bandwidth of more than 7.5%. Low average power consumption of 1.3 mW RMS, has been obtained by biasing the oscillator devices to operate in class-B i.e. VGS = VDD = Vth.
Starting Page	1
Ending Page	6
File Size	673920
Page Count	6
File Format	PDF
ISBN	9781467317108
e-ISBN	9781467317115
e-ISBN	9781467317092
DOI	10.1109/ICSES.2012.6382224
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-09-18
Publisher Place	Poland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Radio frequency Voltage-controlled oscillators Q factor Resonant frequency Transistors Tuning
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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