NDLI: Enhanced Cycle Simulator for MIPS Architecture -- CSMIPSA

Content Provider	IEEE Xplore Digital Library
Author	Arora, H. Rajpurohit, Y.
Copyright Year	2013
Description	Author affiliation: Sch. of Comput. Sci. & Eng., Vellore Inst. of Technol. Univ., Vellore, India (Arora, H.) \|\| Applic. Platform R&D, Genesys Telecom Labs., Chennai, India (Rajpurohit, Y.)
Abstract	Detailed modeling of processors and cycle accurate simulators are essential for today's hardware and software design. These problems are challenging enough by themselves and have seen many previous research efforts. Addressing both simultaneously is even more challenging, with many existing approaches focusing on one over another. In this paper, we describe the simulator designed by us focused on cycle based approach for instruction execution for the reference MIPS®32 Architecture. This simulator models the extensive user interface based interpretation (three tiered) approach for simulating instruction set for MIPS®32 Architecture in complete Object Oriented Paradigm/Design space. It allows the user to examine the internal state of the target machine, such as the values of processor registers during the execution of each instruction, thereby helping to validate the processor design, the compiler design, as well as evaluate architectural design decisions & provides all the quality metrics of an Instruction Set Architecture(ISA) design explicitly.
Sponsorship	IEEE UK/Ireland Sect. C Chapt.
Starting Page	365
Ending Page	373
File Size	457208
Page Count	9
File Format	PDF
ISBN	9781467364218
DOI	10.1109/UKSim.2013.81
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-04-10
Publisher Place	UK
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Object oriented modeling ISA Design Single-Cycle simulation Registers Modeling UI based interpretation Program processors Object-Oriented Paradigm Computer architecture Multi-Cycle simulation Assembly Load modeling Clocks
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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