NDLI: Architectural system modeling for correct-by-construction RTL design

Content Provider	IEEE Xplore Digital Library
Author	Urdahl, J. Stoffel, D. Kunz, W.
Copyright Year	2015
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Univ. of Kaiserslautern, Kaiserslautern, Germany (Urdahl, J.; Stoffel, D.; Kunz, W.)
Abstract	This paper works towards a new design flow in which a design model at an architectural system level is refined into an RTL implementation in such a way that architectural model and RTL implementation stand in a well-defined formal relationship to each other. Functional properties valid at the system level are guaranteed to hold also in the concrete implementation without any additional verification efforts at the RTL. Based on the notion of path predicate abstraction (PPA) introduced in previous work, this paper contributes an "architectural modeling language (AML)" which formalizes the semantics of the architectural description level w.r.t. a PPA. The language is intended to be used only as an intermediate description automatically derived from standardized ESL languages such as SystemC when these descriptions are restricted to a mappable subset. Such an intermediate representation is needed to overcome the limitations of SystemC in precisely defining the semantics of the design model and its interfaces as well as to cope with the overwhelming expressive power of SystemC and the large syntactical diversity it allows. With an AML description of the architectural model as a starting point, the paper will show how properties in a standard language like SVA can be automatically generated that guarantee the correctness of the implementation when proven on the design after all refinement steps in the design and the property set have been completed.
Starting Page	1
Ending Page	8
File Size	252862
Page Count	8
File Format	PDF
e-ISBN	9781467377355
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-09-14
Publisher Place	Spain
Access Restriction	Subscribed
Rights Holder	ECSI
Subject Keyword	Semantics Ports (Computers) Color Syntactics Concrete Integrated circuit modeling Monitoring
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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