NDLI: TLM POWER3: Power estimation methodology for SystemC TLM 2.0

Content Provider	IEEE Xplore Digital Library
Author	Greaves, D. Yasin, M.
Copyright Year	2012
Description	Author affiliation: Computer Laboratory, King Faisal University, Al-Ahasa, Saudi Arabia (Yasin, M.) \|\| Computer Laboratory, University of Cambridge, CB3 0FD, United Kingdom (Greaves, D.)
Abstract	We report on a SystemC add-on library which extends every SystemC module with non-functional data regarding power consumption and physical layout and which accumulates and estimates dynamic energy usage. It supports both phase/mode power modelling and energy-per-transaction logging for TLM (transactional-level modelling). Wiring energy is computed by counting bit-level activity within the TLM generic payload. Each leaf component can also register its physical dimensions to facilitate a wire length estimator that traverses the SystemC model hierarchy using either full placement or Rent's rule estimators. It also supports dynamic voltage islands and inter-chip wiring, where each transaction can consume energy according to the current supply voltage of the relevant islands and the nature of the interconnect. We report on basic peformance from some SPLASH-2 benchmarks running on a modelled OpenRISC quad-core platform.
Starting Page	106
Ending Page	111
File Size	158457
Page Count	6
File Format	PDF
ISBN	9781467312400
ISSN	16369874
e-ISBN	9782953050455
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-09-18
Publisher Place	Austria
Access Restriction	Subscribed
Rights Holder	ECSI
Subject Keyword	Power demand Time varying systems Computational modeling Random access memory Time domain analysis Libraries Payloads
Content Type	Text
Resource Type	Article

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