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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Chaparala, A. Novoa, C. Qasem, A. |
| Copyright Year | 2015 |
| Description | Author affiliation: Ingram Sch. of Eng., Texas State Univ., San Marcos, TX, USA (Novoa, C.) || Dept. of Comput. Sci., Texas State Univ., San Marcos, TX, USA (Chaparala, A.; Qasem, A.) |
| Abstract | The Quadratic Assignment Problem (QAP) is an important combinatorial optimization problem with applications in many areas including operations research and chip design. QAP is known to be NP-hard and requires heuristic approaches for most real data sets. Although many algorithms have been proposed for solving QAPs, few have attempted to exploit the fine-grain data parallelism available on accelerator architectures and none have considered aspects of energy efficiency. In this paper, we present GPU-accelerated implementations of two QAP algorithms. We parameterize each algorithmic variant along several dimensions including thread granularity, occupancy, shared memory usage and register pressure. We develop an autotuning framework that explores this space of execution parameters and yields CUDA binaries that are efficient in terms of both performance and power consumption. We demonstrate the effectiveness of our tuning framework on an Nvidia Tesla K20c. On a series of experiments on the well-known QAPLIB data sets, our autotuned solutions run at least an order-of-magnitude faster than baseline implementations. The experimental results also provide key insight into the performance characteristics of accelerated QAP solvers. In particular, the results reveal that both algorithmic choice and the shape of the input data sets are key factors in finding an efficient implementation. |
| Starting Page | 78 |
| Ending Page | 83 |
| File Size | 933542 |
| Page Count | 6 |
| File Format | |
| e-ISBN | 9781479989379 |
| DOI | 10.1109/HPCC-CSS-ICESS.2015.121 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2015-08-24 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Instruction sets Graphics processing units energy efficiency autotuning Registers Sparse matrices Kernel parallel performance Optimization Tuning |
| Content Type | Text |
| Resource Type | Article |
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