NDLI: Enabling GPU and Many-Core Systems in Heterogeneous HPC Environments Using Memory Considerations

Content Provider	IEEE Xplore Digital Library
Author	Guim, F. Rodero, I. Corbalan, J. Parashar, M.
Copyright Year	2010
Abstract	Increasing the utilization of many-core systems has been one of the forefront topics these last years. Although many-cores architectures were merely theoretical models few years ago, they have become an important part of the high performance computing market. The semiconductor industry has developed Graphical Processing Units (GPU) systems that provide access to many cores (i.e: Larrabee, Fermi or Tesla) that can be used for General Purpose (GP) computing. In this paper, we propose and evaluate a scheduling strategy for GPU and many-core architectures for HPC environments. Specifically, our strategy is a variant of the backfilling scheduling policy with resource sharing considerations. We propose a scheduling strategy that considers the differences between GP processors and GPU computing elements in terms of computational capacity and memory bandwidth. To do this, our approach uses a resource model that predicts how shared resources are used in both GP and GPU/many-core elements. Furthermore, it considers the differences between these elements in terms of performance. First, it models their differences in terms of computational power and how they share the access to the node's memory bandwidth. Second, it characterizes how the processes are allocated to the GPU. Using this resource model, we design the Power Aware resource selection policy, which we combine with the Less Consume scheduling policy. Our strategy tries to allocate jobs aiming at reducing the memory contention and the energy consumption. Results show that the scheduling strategies proposed in this work are able to save over 40\% of energy and improve the system performance up to 30\% with respect to traditional backfilling strategies.
Starting Page	146
Ending Page	155
File Size	379179
Page Count	10
File Format	PDF
ISBN	9781424483358
DOI	10.1109/HPCC.2010.29
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-09-01
Publisher Place	Australia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	DVS Runtime Processor scheduling Computational modeling memory considerations Job Scheduling Bandwidth Resource management GPU Graphics processing unit
Content Type	Text
Resource Type	Article

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