NDLI: FPGA Implementation of the SMS4 Block Cipher in the Chinese WAPI Standard

Content Provider	IEEE Xplore Digital Library
Author	Xianwei Gao Erhong Lu Liqin Xian Hanlin Chen
Copyright Year	2008
Description	Author affiliation: Beijing Electron. Sci. & Technol. Inst., Beijing (Xianwei Gao; Erhong Lu; Liqin Xian; Hanlin Chen)
Abstract	SMS4 is a 32-round block cipher with a 128-bit block size and a 128-bit user key. This paper presents rolling and unrolling field programmable gate array implementation of the SMS4 algorithm, and both the encryption and the decryption algorithms of SMS4 have been implemented on the same FPGA. The rolling design of SMS4 for area requires 1552 ALMs, the maximum operating clock is 139MHz and the corresponding data throughput is about 539 Mbit/s. The unrolling design of SMS4 for speed requires 8373 ALMs, the maximum operating clock is 162 MHz and the corresponding data throughput is about 20736 Mbit/s. Our SMS4 implementation has a good balance between high performance and low complexity in area as a result of taking advantage of certain features present in Straitx II FPGA and some design strategies.
Starting Page	104
Ending Page	106
File Size	249426
Page Count	3
File Format	PDF
ISBN	9780769532882
DOI	10.1109/ICESS.Symposia.2008.76
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-07-29
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Algorithm design and analysis VHDL FPGA Computer architecture Altera Throughput Registers Cryptography SMS4 Field programmable gate arrays Clocks
Content Type	Text
Resource Type	Article

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