NDLI: Implementation of a biologically inspired neuron-model in FPGA

Content Provider	IEEE Xplore Digital Library
Author	Rossmann, M. Hesse, B. Goser, K. Buhlmeier, A. Manteuffel, G.
Copyright Year	1996
Description	Author affiliation: Dortmund Univ., Germany (Rossmann, M.; Hesse, B.; Goser, K.)
Abstract	This paper presents the implementation of a biologically inspired neuron-model. Learning is performed on-line in special synapses based on the biologically proved Hebbian learning algorithm. This algorithm is implemented on-chip allowing an architecture of autonomous neural units. The algorithm is transparent so connections between the neurons can easily be engineered. Due to their functionality and their flexibility only few neurons are needed to fulfil basic tasks. A parallel and a serial concept for an implementation in an FPGA (Field Programmable Gate-Array) are discussed. A prototype of the serial approach is developed in a XILINX FPGA series 3090. This solution has one excitatory, one inhibitory, two Hebbian synapses and one output operating with 8 bit resolution. The internal computation is performed at higher resolution to eliminate errors due to overflow. The Hebbian weights are stored at a precision of 19 bit for multiplication. The prototype works at a clock frequency of 5 MHz leading to an update rate of 333 kCUPS.
Starting Page	322
Ending Page	329
File Size	717275
Page Count	8
File Format	PDF
ISBN	0818673737
ISSN	10861947
DOI	10.1109/MNNFS.1996.493810
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-02-12
Publisher Place	Switzerland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Design engineering High performance computing Neurons Neural networks Prototypes Frequency System-on-a-chip Hebbian theory Field programmable gate arrays Clocks
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
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8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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