NDLI: A multi-channel integrated readout circuit chip for small capacitance sensors

Content Provider	IEEE Xplore Digital Library
Author	Xiang He Fritz, T.A. Knepper, R.W. Mavretic, A.
Copyright Year	2013
Abstract	The design, fabrication, and test results of a multi-channel integrated readout circuit (MIROC) mixed-signal ASIC for low capacitance (<;10pF) solid state sensors arrays are presented in this publication. The chip, fabricated in IBM 0.18 μm 7WL SiGe BiCMOS technology and measuring 4 × 4 mm, contains nineteen analog amplifier channels with pulse-shaping and peak-and-hold detection, three on-chip 8-bit hybrid ADCs, each equipped with an 8-bit parallel-to-serial shift register, and digital control logic for routing any of the channels with a hit to any available ADC. As a highly integrated system requiring minimal external controls, the chip was designed with the intention of significantly reducing cost, volume, power, and mass of the readout system for related applications, and consequently should reduce the development cycle of new instruments. MIROC has a FWHM noise below 20keV. Each channel contains four configurable conversion gain levels, measured to be 3.73mV/fC, 8.59mV/fC, 13.89mV/fC and 21.59mV/fC. In case of silicon detectors, the chip is capable of studying energetic charged particles over the range from 100keV to 6MeV. Measured test results and key characteristics are presented in the paper.
Starting Page	1
Ending Page	6
File Size	529982
Page Count	6
File Format	PDF
ISBN	9781467344777
e-ISBN	9782355000263
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-04-16
Publisher Place	Spain
Access Restriction	Subscribed
Rights Holder	CMP
Subject Keyword	ADC Semiconductor device measurement Peak Tracking and Hold Circuit Noise Charged Particle Detector Linearity Logic gates Pulse Shaping and Measurements Capacitance Charge Sensitive Amplifier Sensor arrays
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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