NDLI: Transport Characteristics of Si Nanowires in Bulk Silicon and SOI Wafers

Content Provider	IEEE Xplore Digital Library
Author	Agarwal, A. Singh, N. Liow, T. Kumar, R. Balasubramanian, N. Kwong, D.L.
Copyright Year	2006
Description	Author affiliation: Institute of Microelectronics, 11 Science Park Road, Science Park II, Singapore 117685, Phone: +65-67705927 Fax: +65-6773 1914 Email: agarwal@ime.a-star.edu.sg (Agarwal, A.)
Abstract	Silicon nanowires (SiNW) were fabricated on bulk Silicon and SOI wafers by means of conventional Si process technology. The nanowires were formed by stress-limited oxidation of Si beams pre-patterned on the wafer. Single or double vertically self-aligned wires were obtained depending on the bulk or SOI wafer used and also on the depth of silicon beam etched. The resulting nanowires exhibit triangular cross-section that can be converted to circular shape by annealing at high temperatures, exploiting the visco-elastic properties of SiO2and Si. Electrical measurements on single nanowire show that the resistance scales with length demonstrating consistent cross-sectional dimension in wires of different length. The nanowires formed on SOI wafers were also characterized as channels in FET configuration, using substrate as gate electrode. This technique can be exploited for realizing several nano-electronics, NEMS and biosensor applications in bulk silicon or SOI wafers, all in a CMOS compatible manner.
Starting Page	67
Ending Page	70
File Size	2117788
Page Count	4
File Format	PDF
ISBN	0780393570
DOI	10.1109/NANOEL.2006.1609690
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-01-10
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Annealing Temperature Shape measurement Wires Length measurement Silicon Oxidation Etching Nanowires Electrical resistance measurement
Content Type	Text
Resource Type	Article

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