NDLI: Heterogeneous high performance computer emulation of a space based radar on-board processor

Content Provider	IEEE Xplore Digital Library
Author	Salama, A. Linderman, R. Rooks, J. Leider, A.
Copyright Year	2004
Abstract	This paper presents the successful emulation of an on-board processor (OBP) to support space based radar (SBR). The emulation is demonstrated on the forty-eight node dual Xeon heterogeneous high performance computer (HHPC) operated by the Air Force Research Laboratory (AFRL) located in Rome, New York. Each node in the HHPC supports one Annapolis Wildstar II board composed of 2 Xilinx Virtex II 6 Million gate field programmable gate arrays (FPGAs). As system complexity increases, debugging the software of tera-scale systems with hundreds to thousands of processors is poorly supported by time consuming simulations. However, the advent of large FPGAs allows a powerful new tool to assist in the architecture development effort - emulation. For the case at hand, the 96 FPGAs of the HHPC are capable of emulating at 8% of the actual system clock speed (20 MHz of 250 MHz) and close to 15% of the 2560 individual processors of the proposed SBR system. Even at this reduced scale, this emulation provides a testing environment roughly a million times more capable than HPC-based simulation for early software bug detection and correction. Further, this framework allows for experimenting with architecture enhancements and changes, and ultimately will ensure a low cost, reliable, fully reprogrammable product produced without re-spins. The embedded system architecture of this SBR OBP is based on AFRL's dual processor, power efficient, programmable, wafer scale signal processor (WSSP). Target tracking and discrimination algorithms were developed and demonstrated on an earlier 96-processor embodiment of this architecture. For SBR, the algorithm set is being extended to include synthetic aperture radar (SAR) image formation and moving target indication (MTI) algorithms.
Starting Page	262
Ending Page	267
File Size	205714
Page Count	6
File Format	PDF
ISBN	0769522599
DOI	10.1109/DOD_UGC.2004.20
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-06-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Military computing High performance computing Spaceborne radar Emulation Laboratories Signal processing algorithms Computer architecture Software systems Software debugging Field programmable gate arrays
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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