NDLI: A Methodology Based on Maximal-Profit Spanning Tree for Designing Application Specific Networks on Chip (ASNOC)

Content Provider	IEEE Xplore Digital Library
Author	Yuan-Long Jeang Chung-Wei Hung Chuen-Muh Chiang
Copyright Year	2006
Description	Author affiliation: Dept. of Inf. Eng., Kun Shan Univ., Tainan (Yuan-Long Jeang)
Abstract	In this paper, a methodology based on a mix-mode interconnection architecture is proposed for constructing application specific networks on chip to minimize the total communication time. The proposed architecture uses a globally asynchronous communication network and a locally synchronous bus (or cross-bar or multistage interconnection network MIN). A complete graph is constructed such that each vertex represents an IP core or a set of IP cores connecting by a locally synchronous bus (or cross-bar or MIN) and each edge has a weight (profit) representing a communication ratio (CR) for each pair of vertices. A maximal-profit spanning tree is constructed to represent the final network on chip. Comparisons on cost and total communication times with the SPIN architecture, mesh architecture, and binary tree architecture using Huffman-coding-like algorithm show that the new methodology has better results
Sponsorship	IEEE ICIC Int. National Natural Sci. Found. of China Beijing Jiaotong Univ. Kaosiung Univ. of Appl. Sci
Starting Page	18
Ending Page	21
File Size	163190
Page Count	4
File Format	PDF
ISBN	0769526160
DOI	10.1109/ICICIC.2006.201
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-08-30
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Costs Network topology Tree graphs Network-on-a-chip Computer architecture Switches Binary trees System recovery System-on-a-chip Joining processes
Content Type	Text
Resource Type	Article

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