NDLI: Proposed FPGA Hardware Architecture for High Frame Rate (≫100 fps) Face Detection Using Feature Cascade Classifiers

Content Provider	IEEE Xplore Digital Library
Author	Hung-Chih Lai Savvides, M. Tsuhan Chen
Copyright Year	2007
Description	Author affiliation: Carnegie Mellon Univ., Pittsburgh (Hung-Chih Lai; Savvides, M.; Tsuhan Chen)
Abstract	Face detection is the first and most crucial step in any face recognition systems with applications to face tracking, recognition and automatic surveillance. AdaBoost based face detection training methods have been proposed for producing a rapidly fast detection implementation compared to other methods using the integral image for evaluating a series of weak classifiers very fast. Current software version implementations can achieve about 15-25 frames per second (fps) with a tunable compromise between detection accuracy and speed. In this paper, a novel hardware architecture design on FPGA based on AdaBoost face training and detection algorithm for detecting faces in high resolution images at high frame rates (>100 fps) is proposed. The proposed architecture can evaluate each sub-window in a single clock cycle, which is the fastest possible speed land is limited by the H/W clock running speed. Thus in this proposed approach, detection speed is independent from the number of weak classifiers implemented. The proposed architecture is verified on Xilinx Virtex-II Pro FPGA platform where experimental results show that the speed and memory outperform previous approaches in literature, achieving 143 fps for image size of 640 by 480 pixels using a single scan window. Parallelizing the scan window can lead to double/triple this speed and is dependent on the gate capacity of the FPGA.
Starting Page	1
Ending Page	6
File Size	5624108
Page Count	6
File Format	PDF
ISBN	9781424415960
DOI	10.1109/BTAS.2007.4401930
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-09-27
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Algorithm design and analysis Computer vision Face recognition Surveillance Computer architecture Hardware Face detection Application software Field programmable gate arrays Clocks
Content Type	Text
Resource Type	Article

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