NDLI: Performance Estimation of a First-Order Sigma-Delta Modulator in a CMOS Image Sensor Using Behavioral Modeling

Content Provider	IEEE Xplore Digital Library
Author	Garduza-González, S.
Copyright Year	2010
Abstract	The system-on-chip of study is a proposed CMOS Image Sensor (CIS) architecture which includes: passive pixel array, digital switches for rows/columns and a first-order single-bit Sigma-Delta Modulator for every four columns. This paper presents the behavioral model of the Sigma-Delta Modulator, to estimate their performance in terms of Signal to Noise Ratio and Dynamic Range. The model starts with an ideal modulator, and then are added noise sources and nonlinear distortions, arose by the light source and the modulator non-idealities. All modeling was developed at system level. The performance obtained with the compartmental model showed good agreement with the temporal measurements obtained directly from CIS. This model allows determining the main noise sources that degrade the performance.
Starting Page	749
Ending Page	753
File Size	564768
Page Count	5
File Format	PDF
ISBN	9781424481491
DOI	10.1109/CERMA.2010.89
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-09-28
Publisher Place	Mexico
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Semiconductor device modeling Noise Modulation Jitter CMOS image sensor Sigma-Delta modulator Photodiodes Photoconductivity behavioral modeling Pixel
Content Type	Text
Resource Type	Article

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Performance Estimation of a First-Order Sigma-Delta Modulator in a CMOS Image Sensor Using Behavioral Modeling