NDLI: Reconfigurable MPSoC versus GPU: Performance, power and energy evaluation

Content Provider	IEEE Xplore Digital Library
Author	Gohringer, D. Birk, M. Dasse-Tiyo, Y. Ruiter, N. Hubner, M. Becker, J.
Copyright Year	2011
Description	Author affiliation: Karlsruhe Institute of Technology (KIT), Karlsruhe, Germany (Birk, M.; Ruiter, N.; Hubner, M.; Becker, J.) \|\| Fraunhofer IOSB, Ettlingen, Germany (Gohringer, D.; Dasse-Tiyo, Y.)
Abstract	Different characteristics of algorithms, perform better or worse on various target hardware. The consequent of this is, that the selection of one suitable hardware, such as Graphic Processing Units (GPU), Field Programmable Gate Arrays (FPGAs) or traditional processor cores is a challenging task for developers. The challenge is to choose the most suitable platform satisfying the requirements of the given application, such as real-time and power- / energy consumption constraints. Due to short time to market pressure, a fast development cycle is also a very important characteristic in industrial applications. This work evaluates the performance, power- /energy consumption and the development effort for three processor-based systems: an FPGA-based multiprocessor platform called RAMPSoC, a GPU and a CPU. Two real-world applications have been selected for this evaluation: 3D Ultrasound Computer Tomography and Object Recognition. The paper presents the realization of the applications on the different target hardware and discusses the results of the power and performance evaluation.
Starting Page	848
Ending Page	853
File Size	1009917
Page Count	6
File Format	PDF
ISBN	9781457704352
e-ISBN	9781457704345
e-ISBN	9781457704338
DOI	10.1109/INDIN.2011.6035003
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-07-26
Publisher Place	Portugal
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Instruction sets Finite impulse response filter Hardware Object recognition Kernel Field programmable gate arrays Graphics processing unit
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in