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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Wong, S. Brandon, A. Anjam, F. Seedorf, R. Giorgi, R. Zhibin Yu Puzovic, N. Mckee, S.A. Sjalander, M. Carro, L. Keramidas, G. |
| Copyright Year | 2011 |
| Description | Author affiliation: Delft University of Technology, Delft, The Netherlands (Wong, S.; Brandon, A.; Anjam, F.; Seedorf, R.) || University of Siena Siena, Italy (Giorgi, R.; Zhibin Yu; Puzovic, N.) || UFRGS, Porto Alegre, Brazil (Carro, L.) || Chalmers University of Technology, Göteburg, Sweden (Mckee, S.A.; Sjalander, M.) || Industrial Systems Institute, Patras, Greece (Keramidas, G.) |
| Abstract | The growing complexity and diversity of embedded systems — combined with continuing demands for higher performance and lower power consumption — place increasing pressure on embedded platforms designers. To address these problems, the Embedded Reconfigurable Architectures project (ERA), investigates innovations in both hardware and tools to create next-generation embedded systems. Leveraging adaptive hardware enables maximum performance for given power budgets. We design our platform via a structured approach that allows integration of reconfigurable computing elements, network fabrics, and memory hierarchy components. Commercially available, off-the-shelf processors are combined with other proprietary and application-specific, dedicated cores. These computing and network elements can adapt their composition, organization, and even instruction-set architectures in an effort to provide the best possible trade-offs in performance and power for the given application(s). Likewise, network elements and topologies and memory hierarchy organization can be selected both statically at design time and dynamically at run-time. Hardware details are exposed to the operating system, run-time system, compiler, and applications. This combination supports fast platform prototyping of high-efficient embedded system designs. Our design philosophy supports the freedom to flexibly tune all these hardware elements, enabling a better choice of power/performance trade-offs than that afforded by the current state of the art. |
| Starting Page | 816 |
| Ending Page | 822 |
| File Size | 743374 |
| Page Count | 7 |
| File Format | |
| ISBN | 9781457704352 |
| e-ISBN | 9781457704345 |
| e-ISBN | 9781457704338 |
| DOI | 10.1109/INDIN.2011.6034998 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-07-26 |
| Publisher Place | Portugal |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Program processors ρ-VEX VLIW processor adaptive embedded platform benchmarking Organizations Benchmark testing Hardware Registers VLIW Field programmable gate arrays |
| Content Type | Text |
| Resource Type | Article |
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