NDLI: Towards an ESL design framework for adaptive and fault-tolerant MPSoCs: MADNESS or not?

Content Provider	IEEE Xplore Digital Library
Author	Cannella, E. Di Gregorio, L. Fiorin, L. Lindwer, M. Meloni, P. Neugebauer, O. Pimentel, A.
Copyright Year	2011
Description	Author affiliation: ALaRI, Faculty of Informatics, University of Lugano, Switzerland (Fiorin, L.) \|\| Silicon Hive BV, High Tech Campus 83, 5656 AG Eindhoven, The Netherlands (Lindwer, M.) \|\| DIEE - Department of Electrical and Electronic Engineering, University of Cagliari, Cagliari, Italy (Meloni, P.) \|\| Computer Systems Architecture Group, Informatics Institute, University of Amsterdam, The Netherlands (Pimentel, A.) \|\| Lantiq Deutschland GmbH, Neubiberg, Germany (Di Gregorio, L.) \|\| Informatik Centrum Dortmund, Joseph-von-Fraunhofer-Str. 20, Dortmund, Germany (Neugebauer, O.) \|\| Leiden Institute of Advanced Computer Science, Leiden University, The Netherlands (Cannella, E.)
Abstract	The MADNESS project aims at the definition of innovative system-level design methodologies for embedded MP-SoCs, extending the classic concept of design space exploration in multi-application domains to cope with high heterogeneity, technology scaling and system reliability. The main goal of the project is to provide a framework able to guide designers and researchers to the optimal composition of embedded MPSoC architectures, according to the requirements and the features of a given target application field. The proposed approach will tackle the new challenges, related to both architecture and design methodologies, arising with the technology scaling, the system reliability and the ever-growing computational needs of modern applications. The methodologies proposed with this project act at different levels of the design flow, enhancing the state-of-the art with novel features in system-level synthesis, architectural evaluation and prototyping. Support for fault resilience and efficient adaptive runtime management is introduced at hardware and middleware level, and considered by the system-level synthesis as one of the optimization factors to be taken into account. This paper presents the first stable results obtained in the MADNESS project, already demonstrating the effectiveness of the proposed methods.
Starting Page	120
Ending Page	129
File Size	987552
Page Count	10
File Format	PDF
ISBN	9781457721236
e-ISBN	9781457721229
DOI	10.1109/ESTIMedia.2011.6088518
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-10-13
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fault tolerance Program processors Emulation Computer architecture Hardware Libraries Field programmable gate arrays
Content Type	Text
Resource Type	Article

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