NDLI: Rapid exploration of multimedia system-on-chips with automatically generated software performance models

Content Provider	IEEE Xplore Digital Library
Author	Kirchsteiger, C.M. Schweitzer, H. Trummer, C. Steger, C. Weiss, R. Pistauer, M.
Copyright Year	2008
Description	Author affiliation: Inst. for Tech. Inf., Univ. of Technol., Graz (Kirchsteiger, C.M.; Schweitzer, H.; Trummer, C.; Steger, C.; Weiss, R.) \|\| CISC Semicond. GmbH, Klagenfurt (Pistauer, M.)
Abstract	A challenge in the design space exploration of todays' multimedia system-on-chip (SoC) designs is to rapidly evaluate the large number of different processor types. This limitation is resolved by our methodology, originated from the SIMBA1 project. It automatically generates a Sys- temC performance model of the software code with respect to the chosen processor type. The generated performance model consists of the original software C-code annotated with SystemC wait statements to consider the execution time on the target processor. These wait statements are automatically determined by the target cross-compiler's assembler code and the processor datasheet and consider also memory accesses and pipeline effects. In our experiments we automatically generate both a performance model of an ARM and a TI processor. This only requires the target cross-compiler and the processor datasheet and is widely applicable to various processor types. We show that our models can be used easily to compare the software performance on these platforms. We also demonstrate that the models can be smoothly integrated into an existing multimedia SoC for a rapid software-driven architecture exploration.
Starting Page	19
Ending Page	24
File Size	303172
Page Count	6
File Format	PDF
ISBN	9781424426126
DOI	10.1109/ESTMED.2008.4696988
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-10-23
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Software libraries Assembly systems Multimedia systems Pipelines Software performance Computer architecture Space exploration System-on-a-chip Informatics Delay
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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