NDLI: A queuing-theoretic performance model for context-flow system-on-chip platforms

Content Provider	IEEE Xplore Digital Library
Author	Beidas, R. Jianwen Zhu
Copyright Year	2004
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada (Beidas, R.; Jianwen Zhu)
Abstract	Few analytical performance models that relate performance figure of merit to architectural design decisions are reported in recent studies of network-on-chip, which prevents the development of effective system-level synthesis techniques. We propose an analytical performance model based on queuing theory for a network-on-chip platform recently reported, which features an extremely simple programming model, while providing superior performance measures when compared with alternative architectures. We developed a multi-processor simulation framework, which can simulate an application at the instruction set level given an architecture configuration, to validate the analytical performance model. The accuracy and applicability of the proposed model is illustrated by two real-life applications, namely an SSL security acceleration processor and MP3 decoder.
Starting Page	21
Ending Page	26
File Size	477072
Page Count	6
File Format	PDF
ISBN	0780386310
DOI	10.1109/ESTMED.2004.1359697
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-09-06
Publisher Place	Sweden
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Analytical models Network-on-a-chip Network synthesis Performance analysis System-on-a-chip Security Acceleration Queueing analysis Digital audio players Context modeling
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A queuing-theoretic performance model for context-flow system-on-chip platforms

A Performance Analytical Approach Based on Queuing Model for Network-on-Chip

Modeling and Performance Analysis of Network on Chip Based on Improved Asymmetric Multi-channel Router

Transient queuing models for input-buffered routers in Network-on-Chip

An accurate and efficient performance analysis approach based on queuing model for network on chip

Efficient Parallel Queuing System Simulation

QSYN: Queueing networks synthesis for system on chip

A queuing network analysis model in emergency departments

A comprehensive power-performance model for NoCs with multi-flit channel buffers

A queuing-theoretic performance model for context-flow system-on-chip platforms

Similar Documents

A queuing-theoretic performance model for context-flow system-on-chip platforms

A Performance Analytical Approach Based on Queuing Model for Network-on-Chip

Modeling and Performance Analysis of Network on Chip Based on Improved Asymmetric Multi-channel Router

Transient queuing models for input-buffered routers in Network-on-Chip

An accurate and efficient performance analysis approach based on queuing model for network on chip

Efficient Parallel Queuing System Simulation

QSYN: Queueing networks synthesis for system on chip

A queuing network analysis model in emergency departments

A comprehensive power-performance model for NoCs with multi-flit channel buffers

A queuing-theoretic performance model for context-flow system-on-chip platforms