NDLI: Array Processors for Viterbi Decoder

Content Provider	IEEE Xplore Digital Library
Author	Devaraj, A.S. Avessta, N.
Copyright Year	2005
Description	Author affiliation: Dept. of Inf. Technol., Turku Univ. (Devaraj, A.S.; Avessta, N.)
Abstract	Wireless receivers are often characterized as portable and battery operated. As such, they are bound by a tight set of constraints such as power consumption, area usage, and throughput speed. Parallel implementation of operations increases the speed of computation without an undue increase in lock frequency. Thus, high throughput is achieved without excessive power consumption. The apparent tradeoff in throughput improvement, of parallel implementation, is the larger area usage. Hence, there is a need to find an optimal implementation in terms of area, speed and complexity. In this paper, an exhaustive set of parallel implementations of Viterbi decoder is developed, by different arrangements of processing elements (PEs) and schedules. Objective comparison among various implementations is performed to select the optimal implementation
Starting Page	447
Ending Page	451
File Size	732354
Page Count	5
File Format	PDF
ISBN	078039206X
DOI	10.1109/ISWCS.2005.1547740
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-09-05
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Energy consumption Viterbi decoder Throughput Decoding Spatial-temporal mapping Concurrent computing Wireless communication Viterbi algorithm Space technology Parallel processing Frequency design space exploration array processor Clocks
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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