NDLI: Development of a simulation Environment for Vehicular communications, implementation of FEC coding chain in Xilinx FPGA based on IEEE 802.11p standard

Content Provider	IEEE Xplore Digital Library
Author	Kiokes, G. Uzunoglu, N.K.
Copyright Year	2009
Description	Author affiliation: Microwave and Fiber Optics Laboratory, School of Electrical and Computer Engineering, National Technical University of Athens, Greece (Kiokes, G.; Uzunoglu, N.K.)
Abstract	This work presents the performance analysis and optimization of the IEEE 802.11p Physical layer and the implementation of the Forward Error Correction (FEC) coding chain on Xilinx FPGA hardware. A MATLAB simulation is carried out in order to analyze baseband processing of the transceiver. IEEE 802.11p Wireless Access in the Vehicular Environment defines modifications to IEEE 802.11 to support Intelligent Transportation Systems applications. Performance analysis of Physical layer model has been estimated into different propagation conditions (AWGN, Ricean and Rayleigh fading). Two different coding schemes and a different value of guard interval has been employing in the model in order to optimize its performance. The coding chain in the transmitter with and without the two coding schemes has been implemented in a FPGA from Xilinx using the System Generator tool-flow for fast prototyping.
Starting Page	1
Ending Page	3
File Size	5177613
Page Count	3
File Format	PDF
ISBN	9781424444403
DOI	10.1109/WOWMOM.2009.5282403
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-06-15
Publisher Place	Greece
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Forward error correction Physical layer Hardware Performance analysis Standards development Mathematical model MATLAB Field programmable gate arrays Intelligent transportation systems Communication standards
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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