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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Shan Chang-hong Chen Zhong-ze Jiang Jin-xiong |
| Copyright Year | 2009 |
| Abstract | Based on synthesizing most sorts of phase/frequency locking mechanisims respectively shown in different conventional all digital phase-locked loop (all DPLL) systems, a novel all DPLL, which is with higher performances on wideband frequency tracking and also possesses a balance mechanisim for improving system performance on noise reduction as well as shortening time for arriving at a synchronous state, is proposed. The system has a parameters adaptation enginery, which ensures the synchronization of the phase/frequency of the output signal with that of input when a wide range of variance in phase/frequency of input signal occurs. The system is designed by using Very-High-Speed Integrated Circuit Hardware Description Language (VHDL) and implemented on a Field Programmable Gate Array (FPGA) chip. And the simulation and experimental results show that the system possesses good robustness property, for it will return to its stable state within 4 clock cycles if input signal gives a frequency jump from 400 KHz to 160 KHz. Besides, it also takes on excellent performance on noise reduction. In a word, the system is characteristic of its simple circuit structure, excellent adaptation and robustness properties, and it is prone to system integration and thus can be packed as an IP core for SoC applications. |
| Starting Page | 460 |
| Ending Page | 463 |
| File Size | 216689 |
| Page Count | 4 |
| File Format | |
| ISBN | 9780769537450 |
| DOI | 10.1109/HIS.2009.306 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2009-08-12 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Tracking loops Frequency synthesizers Noise reduction FPGA All Digital Phase-Locked Loop (all DPLL) Phase locked loops VHDL System performance Filter Very high speed integrated circuits Noise robustness Frequency synchronization Wideband Field programmable gate arrays Wideband Frequency Tracking |
| Content Type | Text |
| Resource Type | Article |
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