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Content Provider | IEEE Xplore Digital Library |
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Author | Qian Min Zhu Jing Cao Yunpeng Yang Cuijun |
Copyright Year | 2011 |
Abstract | The embedded Ethernet is widely applied, and its research is very important. In this paper, the embedded Ethernet controller is designed. The Ethernet MAC sublayer protocol and the architecture of Ethernet data frame are briefly introduced. The 10/100Mbps adaptive Ethernet controller is designed with Verilog-HDL, which includes the WISHBONE bus interface, Tx/Rx module, flow control module, etc. The testing vectors are constructed and the whole design is simulated in ModelSim PLUS 6.4SE tools and successfully verified by ALTERA FPGA. The result of logic simulation and FPGA physical verification of board level indicate that the related function of 10/100Mbps adaptive Ethernet controller is realized. |
Starting Page | 1 |
Ending Page | 3 |
File Size | 312727 |
Page Count | 3 |
File Format | |
ISBN | 9781424462506 |
ISSN | 21619654 |
e-ISBN | 9781424462520 |
DOI | 10.1109/wicom.2011.6040465 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2011-09-23 |
Publisher Place | China |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Process control Media Media Access Protocol Registers System-on-a-chip Field programmable gate arrays |
Content Type | Text |
Resource Type | Article |
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