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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Jianwen Zhang Min Xiao Lin Wang |
| Copyright Year | 2008 |
| Description | Author affiliation: Dept. of Commun. Eng., Xiamen Univ., Xiamen (Jianwen Zhang; Min Xiao; Lin Wang) |
| Abstract | In order to implement an encoder of q-ary LDPC codes, the RU algorithm proposed in [1] is applied in encoder design of q-ary LDPC codes in this paper. A new preprocessing algorithm helping to producing sparser inverse matrix $T^{-1}$ is presented, which results in better tradeoff strategy between resources and throughput with proper implementation module in $T^{-1}.$ The feasibility and effect of the algorithm is verified through a hardware implementation of a random 4-ary LDPC codes on a Xilinx spartan3s1500. The encoder runs at 129 MHz and has a throughput of 36.8 Msymbol/s, namely, 73.6 M codeword bits per second. Only by proper combination in preprocessing algorithm and architecture, it is found that the throughput beyond 100 Mb/s is also possible. |
| Starting Page | 1236 |
| Ending Page | 1239 |
| File Size | 939486 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424420636 |
| DOI | 10.1109/ICCCAS.2008.4657991 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2008-05-25 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Algorithm design and analysis Signal processing algorithms Computer architecture Throughput Hardware Sparse matrices Clocks |
| Content Type | Text |
| Resource Type | Article |
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