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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Liu Qing Peng Hong |
| Copyright Year | 2007 |
| Description | Author affiliation: UESTC, Chengdu (Liu Qing) |
| Abstract | In this paper, a new architecture is proposed for high-speed digital down conversion (DDC) for communication signal processing. The proposed architecture integrates conventional polyphase filter with polyphase mixer (PFPM) for decimation in DDC. The PFPM architecture decreases both the rate of the mixer and filter and can process the signals with a very high sample rate, which cannot be realistically implement in conventional DDC in a general purpose processor (GPP) such as field programmable gate array (FPGA) or digital signal processor (DSP). Simulation and experiment have been done to verify the availability of the PFPM architecture. These results show that the proposed PFPM architecture reduces the operation rate of the mixer and well agrees with the conventional DDC architecture. |
| Starting Page | 319 |
| Ending Page | 322 |
| File Size | 1054016 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424414734 |
| DOI | 10.1109/ICCCAS.2007.6250851 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-07-11 |
| Publisher Place | Japan |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Mixers |
| Content Type | Text |
| Resource Type | Article |
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