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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Ning Xu Feng Huang Yuchun Ma Zhonghua Jiang Xianlong Hong |
| Copyright Year | 2007 |
| Description | Author affiliation: Wuhan Univ. of Technol., Wuhan (Ning Xu; Feng Huang) |
| Abstract | The trends in VLSI design go toward increased component integrated density and higher power consumption. The thermal management plays a prominent role in recent years. The maximum temperature of a block in a chip depends, however, not only on its own power density, but also on the power density of the adjacent blocks. Consequently, the layout of architectural blocks, or a particular floorplan selected for a given chip, can affect the maximum temperature of the chip considerably. Our floorplanner simultaneously considers high performance, thermal reliability, area, and interconnect length and provides various tradeoff points. We use two-stage optimization in microarchitectural floorplanning so that the trade-off between performance and the thermal effects can be well controlled. An Alpha microprocessor is used as an example to demonstrate the effect of our floorplanner. The experimental results show that our floorplanner is stable which can simultaneously optimize the performance and temperature of the design. |
| Starting Page | 1158 |
| Ending Page | 1162 |
| File Size | 3485916 |
| Page Count | 5 |
| File Format | |
| ISBN | 9781424414734 |
| DOI | 10.1109/ICCCAS.2007.4348252 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-07-11 |
| Publisher Place | Japan |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Computer science Energy consumption Temperature dependence Microarchitecture Microprocessors Very large scale integration Thermal management Power system reliability Delay Clocks |
| Content Type | Text |
| Resource Type | Article |
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