NDLI: Ray Tracing on the Cell Processor

Content Provider	IEEE Xplore Digital Library
Author	Benthin, C. Wald, I. Scherbaum, M. Friedrich, H.
Copyright Year	2006
Description	Author affiliation: inTrace Realtime Ray Tracing GmbH (Benthin, C.)
Abstract	Over the last three decades, higher CPU performance has been achieved almost exclusively by raising the CPU's clock rate. Today, the resulting power consumption and heat dissipation threaten to end this trend, and CPU designers are looking for alternative ways of providing more compute power. In particular, they are looking towards three concepts: a streaming compute model, vector-like SIMD units, and multi-core architectures. One particular example of such an architecture is the cell broadband engine architecture (CBEA), a multi-core processor that offers a raw compute power of up to 200 GFlops per 3.2 GHz chip. The cell bears a huge potential for compute-intensive applications like ray tracing, but also requires addressing the challenges caused by this processor's unconventional architecture. In this paper, we describe an implementation of realtime ray tracing on a cell. Using a combination of low-level optimized kernel routines, a streaming software architecture, explicit caching, and a virtual software-hyperthreading approach to hide DMA latencies, we achieve for a single cell a pure ray tracing performance of nearly one order of magnitude over that achieved by a commodity CPU
Starting Page	15
Ending Page	23
File Size	724408
Page Count	9
File Format	PDF
ISBN	1424406935
DOI	10.1109/RT.2006.280210
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-09-18
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	multi-core Energy consumption Multicore processing Software architecture Cell processor Computer architecture Computer applications Ray tracing Application software Kernel Engines Clocks
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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