NDLI: Bias dependent and scalable small-signal modeling of pseudomorphic HEMTs

Content Provider	IEEE Xplore Digital Library
Author	Verma, A.K. Chaturvedi, S. Bhat, K.M. Saravanan, G.S. Muralidharan, R.
Copyright Year	2009
Description	Author affiliation: Gallium Arsenide Enabling Technology Centre, Hyderabad (A.P.) - 500069, India (Chaturvedi, S.; Bhat, K.M.; Saravanan, G.S.; Muralidharan, R.) \|\| Institute of Technology, Banaras Hindu University, Varanasi (U.P.) - 221005, India (Verma, A.K.)
Abstract	Results of small-signal modeling of 0.5um gate length pseudomorphic HEMTs are presented here. Modeling included scalability with respect to number of gate fingers, gate width and gate bias dependence of Equivalent Circuit Parameters (E.C.Ps). p-HEMTs with gate widths of 100 µm and 150 µm, each with varying number of gate fingers (2, 4, 6) keeping all other structural parameters constant were fabricated for this study. To find small-signal E.C.Ps we used method proposed by Dambrine et.al. [2] and White-Healy [3]. On-wafer measurement of S-parameters for all devices was done from 100 MHz to 40 GHz under different bias-conditions. Using this data, all the E.C.Ps were then extracted for each device, at various gate-biases and Vds = 3V. Finally we have a model that can give the E.C.Ps of any device we fabricated, given the gate-bias, number of gate-fingers and gate-width. This equivalent circuit can be used to generate S-parameters of devices with good accuracy in the whole frequency range of measurement.
Starting Page	1
Ending Page	4
File Size	534814
Page Count	4
File Format	PDF
ISBN	9781424438310
DOI	10.1109/EDST.2009.5166138
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-06-01
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Gold scaling PHEMTs HEMT Etching Roentgenium Electrical resistance measurement Equivalent Circuit Fabrication Fingers HEMTs Scattering parameters p-HEMT small signal model Equivalent circuits
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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